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An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs

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4 Author(s)
Amaral, P. ; Faculdade de Ciencias e Tecnologia, Campus da Faculdade de Ciencias e Tecnologia, Caparica, Portugal ; Goes, J. ; Paulino, N. ; Steiger-Garcao, A.

This paper presents an improved low-voltage low-power CMOS comparator suitable for high-speed pipeline ADCs. Simulated results of the proposed circuit in a 0.35 μm standard CMOS technology operating at supply voltages within the range of 1.0-1.5 V show that this comparator achieves low offset, reduced kickback noise, high mean-time to failure and exhibits low-power dissipation at very high-speed operation.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference: