By Topic

A single-chip real-time programmable video signal processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Lingfeng Li ; Dept. of Electron. Eng., Tsinghua Univ., Beijing, China ; Danian Gong ; Yun He

In this paper, we describe a cost-efficient programmable video signal processor (PVSP) to implement various video encoding and decoding schemes. Hierarchical (two level) programmable control architecture, flexible memory address mapping strategies and a programmable VLC/VLD module are applied in order to achieve sufficient programmability. Thus, PVSP can support various video compression algorithms and standards, such as MPEG-1, MPEG-2 H.263, and MPEG-4. Meanwhile, to improve the throughput of this codec system, some paralleling approaches are exploited on different levels, which include pipeline, tree adder, and SIMD (single instruction stream, multiple data streams). PVSP is estimated to have approximately 320 k gates and it can accomplish MPEG-2 MP@ML encoding in real-time at a frequency of 133 MHz.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference:

2002