By Topic

Current-sensing completion detection method for standard cell based digital system design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Lampinen, H. ; Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland ; Vainio, O.

This paper shows how the current-sensing completion detection (CSCD) method can be applied for standard cell based digital system design. With the proposed method, conventional synchronous CMOS logic circuit blocks can easily be modified for self-timed asynchronous operation. To illustrate the usage of the method a self-timed CSCD multiplier-accumulator (MAC) was constructed. Simulation results and VHDL synthesized layouts of the CSCD MAC show that the CSCD method and the various proposed design practices can be used for the construction of self-timed asynchronous logic systems.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

Date of Conference:

2002