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In this paper, a pulse-clocked double edge-triggered D-flip-flop (PDET) is proposed. The PDET uses a split-output TSPC latch and when clocked by a short pulse train acts like a double edge-triggered flip-flop. The new double edge-triggered flip-flop uses only eight transistors with only one N-type transistor being clocked. Compared to other double edge-triggered flip-flops, PDET offers advantages in terms of speed, power, and area. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge-triggered flip-flops. Simulations are performed using HSPICE in CMOS 0.5 μm technology. This design is suitable for high-speed, low-power CMOS VLSI design applications.