A new methodology for the statistical analysis of VLSI CMOS circuits and its application to flash memories

In this paper a new CAD methodology for the statistical analysis of VLSI CMOS circuits is presented. A novel very accurate position-dependent mismatch model has been implemented into a complete CAD tool. The tool is fully integrated in an environment of commercial tools and it has been experimented on in the Flash Memory CAD Group in STMicroelectronics. As an example of application, a bandgap test circuit has been considered and the results have been compared with experimental data. This methodology has also been applied to the read path of a complex flash memory produced by STMicroelectronics, consisting of about 16,000 MOSFETs. Measurements of electrical performances have confirmed the accuracy of the proposed simulation flow and models.