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In this paper, we present a timing-driven architecture and component selection method for high-performance FIR designs. We develop an FIR generator that can generate Verilog-based RTL design specifications by determining the FIR structure, component types and their delay budgets subject to satisfying the given timing constraints. By integrating the FIR generator and a number of commercial RTL/logic and physical synthesis tools, we develop a design environment for high-performance FIR designs. Experimental results have shown that our proposed design flow can generate FIR designs ranging from 100 MHz to 300 MHz on the fly.