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Task graph transformation to aid system synthesis

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2 Author(s)
Vallerio, K.S. ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Jha, N.K.

The increasing complexity of real-time embedded systems along with the short time-to-market for most of their applications have led designers to develop increasingly sophisticated algorithms and tools for system-level synthesis. At this level, coarse-grained tasks, such as discrete cosine transforms, are assigned and scheduled on general-purpose processors, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). Hardware-software co-synthesis forms in important sub-problem of system-level synthesis in which price and power are frequently optimized under real-time constraints. This paper proposes a pre-processing step to aid system-level synthesis and is independent of both the targeted cosynthesis tool and its underlying algorithm. Experimental results show that using this methodology can reduce system price (power) by up to 84% (67%) and 12% (16%) on average while reducing co-synthesis tool run-time by 29%.

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Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:4 )

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