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0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems

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2 Author(s)
Shen, E. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Kuo, J.B.

This paper reports a novel 0.8 V content addressable memory (CAM) cell circuit with a fast tag-compare capability using the bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology following the SOI DTMOS technology for low-voltage VLSI systems. Using four PMOS devices with their body controlled dynamically in the tag-compare portion, this CAM cell, which is built in standard bulk CMOS technology using the BP-DTMOS technique, has a faster tag-compare operation at a supply voltage of 0.8 V as compared to the one not using the BP-DTMOS technique.

Published in:
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:4 )

Date of Conference: 2002

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