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This paper analyzes the output phase-skew effects related to practical sample-and-hold embedding in high-speed, time-interleaved sampled-data systems. Closed-formed expressions are presented and verified by numerical computer simulations. Special design techniques and layout issues for reducing both the random process and systematic mismatches are presented through a real application of a low phase-skew clock generation circuit that is used for a very high-frequency SC multirate filter with 320 MHz output sampling rate. Measurement results (skew noise tones <-72 dBc) further verify the proposed techniques.