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A wide-range and fixed latency of one clock cycle delay-locked loop

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3 Author(s)
Hsiang-Hui Chang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Jyh-Woei Lin ; Shen-Iuan Liu

A wide-range delay-locked loop (DLL) with a fixed latency of one clock cycle is proposed. The phase selection circuit and the start-controlled circuit are used for this DLL to enlarge the operating frequency range and eliminate the harmonic locking problems. The operating frequency range of the DLL can be from 1/TDmin to 1/(N×TDmax), where TDmin and TDmax are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line theoretically. The prototype chip is fabricated in a 0.35-um 1P3M CMOS process. The measurement results exhibit the proposed DLL can operate from 6 MHz to 130 MHz and the latency of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter doesn't exceed 25 ps. The DLL occupies an active area of 880-um×515-um and consumes a maximum power of 132 mW at 130 MHz

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:3 )

Date of Conference:

2002