By Topic

Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 μm CMOS technologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sayed, M. ; Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada ; Badawy, W.

This paper presents a performance analysis of single-bit full-adder cells using 0.18, 0.25, and 0.35 μm CMOS technology. Thirty-one single-bit full adder cells have been prototyped and simulated for power consumption, delay and charging capability. A comprehensive analysis is presented that studies the performance of the single-bit full adder cells using three different CMOS technologies.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:3 )

Date of Conference:

2002