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Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 μm CMOS technologies

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2 Author(s)
Sayed, M. ; Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada ; Badawy, W.

This paper presents a performance analysis of single-bit full-adder cells using 0.18, 0.25, and 0.35 μm CMOS technology. Thirty-one single-bit full adder cells have been prototyped and simulated for power consumption, delay and charging capability. A comprehensive analysis is presented that studies the performance of the single-bit full adder cells using three different CMOS technologies.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:3 )

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