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Testability of path history memories with register-exchange architecture used in Viterbi-decoders

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3 Author(s)
Meier, S.R. ; Corporate Dev., Infineon Technol. AG, Munich, Germany ; Steinert, M. ; Buch, S.

Viterbi decoders with; register-exchange path-history contain a large number of registers and multiplexers. Insertion of scan-path registers for testing purposes would generate overhead in terms of area and power-consumption. To avoid scan-registers a, methodology is presented, that allows controlling the already available multiplexers in such a way, that the registers form non-merging chains that can be included in scan-paths.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:3 )

Date of Conference:

2002