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A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-μm CMOS

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4 Author(s)
J. Talebzadeh ; Dept. of Electr. & Comput. Eng., Tehran Univ., Iran ; M. R. Hasanzadeh ; M. Yavari ; O. Shoaei

This paper describes a 10-bit 150 MS/s CMOS parallel pipeline ADC. The converter includes four parallel interleaved pipeline A/D converters with analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators that match the offsets and gains of time-interleaved ADC channels. With monolithic analog background calibration, the SNDR in all corner cases (SS, SF, FS, FF, and TT) and temperature between -40°C to 85°C is better than 57 dB. The power consumption is 1200 mW at a 3.0 V supply voltage. This work is achieved in a 0.6 μm CMOS process.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:3 )

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