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The implementation of a soft-output Viterbi decoder for an eight-state duo-binary code is described. This decoder is to be used in a turbo-decoder for convolutional codes. The implementation was made with the SYNOPSYS environment and targeted an ASIC 0.18 μm technology. The layout obtained has a working frequency of 150 MHz and thus an output data rate of 300 Mbits/s.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on (Volume:1 )
Date of Conference: 2002