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Built-in self-test scheme for on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard

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2 Author(s)
Acevedo, G.O.D. ; Klipsch Sch. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA ; Ramirez-Angulo, J.

This paper presents a testing scheme for analog and mixed-signal circuitry compatible with the IEEE 1149.4 mixed-signal test bus standard. An innovative self-diagnostic method called VDDQ is proposed. The proposed method performs a pass or fail function which sequentially senses quiescent voltage on several nodes of the circuit under test and compares them with their nominal value. The output is a digital flag that passes or fails the nodes accessed. Simulation results are provided for the flag and amplifier circuit used for the design of the testing circuit. Through simulations this test has performed testing one node every millisecond. This testing scheme is at least 12 times faster than currently used methods in industry, which average to 5000 nodes per minute. This will potentially allow a defect free IC to enter the market in significantly less time than with conventional testing methods.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:1 )

Date of Conference:

2002