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The digital front-end electronics for the space-borne INTEGRAL-SPI experiment: ASIC design, design for test strategies and self-test facilities

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9 Author(s)
Cordier, B. ; DSM/DAPNIA, CEA, Centre d''Etudes Nucleaires de Saclay, Gif-sur-Yvette, France ; Donati, M. ; Duc, R. ; Fallou, J.L.
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The flight model of the Digital Front-End Electronics (DFEE) of the gamma-ray spectrometer SPI has been recently integrated on the INTEGRAL satellite spacecraft. The processing core of the DFEE is based on a dedicated Application Specific Integrated Circuit (ASIC). We report on the unified design and test methodology that was deployed to cover the entire life cycle of this subsystem, from initial design simulation to operational self-test and diagnosis operations after launch. Strong emphasis is put on the ASIC design-for-test strategies, from VHDL simulation and test bench validation to full scan fabrication test coverage and in-flight self-test capability.

Published in:

Nuclear Science Symposium Conference Record, 2001 IEEE  (Volume:1 )

Date of Conference:

4-10 Nov. 2001

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