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Optimum architecture for input queuing ATM switches

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2 Author(s)
S. P. Majumder ; Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India ; R. Gangopadhyay

An input queueing ATM switch architecture employing the contention resolution called 'scheduling algorithm' is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.

Published in:

Electronics Letters  (Volume:27 ,  Issue: 7 )