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Lead-free wafer level-chip scale package: assembly and reliability

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3 Author(s)
V. Patwardhan ; Nat. Semicond. Corp., Santa Clara, CA, USA ; N. Kelkar ; L. Nguyen

This paper discusses the reliability testing results of a lead-free version of the micro SMD, National Semiconductor's Wafer Level-Chip Scale Package (WL-CSP). The micro SMD, a true wafer scale package has proven to be highly adaptable in the conventional assembly process, requiring no special considerations during the surface mount assembly operation. The current micro SMD utilizes standard Sn/Pb solder bumps as the interconnect medium. Based on evaluations of the various options available for the lead-free solder, micro SMD devices bumped with Sn/Ag/Cu solder were tested during this evaluation. There are two bump sizes currently available for the micro SMD package, a 170-micron bump diameter and a 300-micron bump diameter. This paper addresses the impact of board assembly conditions, package solder type, package bump size, and thermal cycling profiles on the reliability of the lead-free WL-CSPs. This paper will address the initial evaluations on the 170-micron bumped micro SMD packages. Results of this work are used to determine viable combinations of lead-free and eutectic solder. The lead-free version of the micro SMD is in synch with the next packaging evolutionary stage toward a lead-free assembly process.

Published in:

Electronic Components and Technology Conference, 2002. Proceedings. 52nd

Date of Conference:

2002