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Assembly process induced stress analysis for new FLMP package by 3D FEA

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4 Author(s)
Yong Liu ; Fairchild Semicond. Corp., South Portland, ME, USA ; Irving, S. ; Tumulak, M. ; Cabahug, E.A.

The objective of this paper is to determine what stresses are induced while manufacturing the flip chip in leaded and molded package (FLMP), and to determine potential design weaknesses. A finite element framework is established for processing mechanics through strategy, methodology and virtual simulation platform. The assembly process induced stress modeling of FLMP is investigated by 3D non-linear finite element analysis. The material constitutive relations, algorithms and convergence strategies are discussed. Two major assembly processes: flip chip attach and die clamping in molding, will be targeted. 3D thermal viscoplastic, creep and plastic large deformation finite element analysis is used to simulate the flip chip attach process during solder reflow and the clamping process in molding.

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Electronic Components and Technology Conference, 2002. Proceedings. 52nd

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