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Sequential Circuit Test Generator (STG) benchmark results

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2 Author(s)
Wu-Tung Cheng ; AT&T Bell Lab., Princeton, NJ, USA ; Davidson, S.

The authors report on the results of running a version of the Sequential Circuit Test Generator (STG3) on the ISCAS-89 sequential circuit benchmarks. First, they present a brief history of STG and briefly describe the algorithms used. They then describe the conditions under which the experiments were run and give the benchmark results. No particular problems were encountered when running STG3 on the benchmark circuits, except for those circuits with many untestable faults. STG3 determines that faults are undetectable fairly quickly, taking only 0.98 s on a totally untestable circuit. The major problem with the circuits considered untestable was in initializing the circuit state

Published in:

Circuits and Systems, 1989., IEEE International Symposium on

Date of Conference:

8-11 May 1989