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An integrated building block for fast digital filtering

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3 Author(s)
V. Rebmann ; Inst. fuer Netzwerk- und Systemtheorie, Stuttgart Univ., West Germany ; J. Heinrich ; E. Luder

A 2.4-μm CMOS chip is presented for realizing a programmable building block for second-order recursive digital filters. All the fabrication steps lend themselves to high-volume production. Using a fast algorithm, a highly parallel computing scheme, and new algorithmic circuits, the chip allows for a maximum clock frequency of 18 MHz, thus being able to compute every second-order filter function in 56 ns with internal 16-bit fixed-point precision. By cascading several chips, filters of higher degree can be obtained without loss of speed

Published in:

Circuits and Systems, 1989., IEEE International Symposium on

Date of Conference:

8-11 May 1989