By Topic

A new multiple-function logic family

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Y. K. Tan ; Dept. of Electr. Eng., Nat. Univ. of Singapore, Kent Ridge ; Y. C. Lim ; C. Y. Kwok ; C. H. Ling

A novel technique is presented for the design of a multiple-function logic (MFL) circuit which generates several Boolean function simultaneously and shares the transistors implementing the common subexpression of these Boolean functions. For certain circuits, this approach requires fewer transistors and reduces the gate delays compared with the conventional approach where the common subexpression is implemented as a new intermediate function, shared by other gates to generate the required outputs. The application of the technique to a CMOS domino logic 4-b carry-lookahead generator and an nMOS 1-of-8 decoder results in savings of 45.0% and 42.5%, respectively, in the number of transistors needed

Published in:

Circuits and Systems, 1989., IEEE International Symposium on

Date of Conference:

8-11 May 1989