A parallel implementation of nonlinear steady state analysis based on time-domain Newton-Raphson algorithm

A parallel implementation of the time-domain Newton-Raphson algorithm is presented. A theoretical expression for speedup was obtained, and simulations were made of several sample circuits. There is a fairly good agreement between the theoretically expected and simulated speedups. It has been shown that a speedup of up to (M-1) can be attained on M processors. Average processor utilization is introduced to analyze the processor load imbalance, and the improvement attained by the proposed method is analyzed in terms of processor utilization.<
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