A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell

First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words × 8-bits FIFO memory test chip, fabricated with a 0.6-μm CMOS process (a short effective channel length of 0.35 μm is available for both the nMOS and pMOS), has demonstrated the 140-MHz operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 μW and that at 100-MHz dual-port operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern)