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A CMOS RF power amplifier with parallel amplification for efficient power control

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3 Author(s)
A. Shirvani ; Center for Integrated Syst., Stanford Univ., CA, USA ; D. K. Su ; B. A. Wooley

This paper introduces a CMOS radio-frequency (RF) power amplifier that uses parallel amplification to provide high efficiency over a broad range of output power. Three binary-weighted class-F unit amplifiers act in conjunction with an efficient power-combination network to provide a digital-to-analog conversion between a 3-b control signal and the amplitude of the output RF signal. The power-combination network is based on quarter-wavelength transmission lines that also serve as class-F harmonic terminations. A pMOS switch to the positive supply rail is used to avoid power dissipation when a unit amplifier is shut down. The parallel-amplifier architecture, integrated in a 0.25-μm CMOS technology, occupies an active die area of 0.43 mm2, operates at 1.4 GHz from a 1.5-V supply, and provides an output power adjustment range of 7-304 mW. The amplifier achieves a maximum power-added efficiency (PAE) of 49% and maintains a PAE of greater than 43% over the range of 100-300 mW

Published in:

IEEE Journal of Solid-State Circuits  (Volume:37 ,  Issue: 6 )