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Avoiding initialization misses to the heap

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3 Author(s)
J. A. Lewis ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; B. Black ; M. H. Lipasti

This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers invalid data. By tracking the initialization of dynamic memory allocations, it is possible to identify store instructions that miss the cache and would fetch uninitialized heap data. The data transfers associated with these initialization misses can be avoided without losing correctness. The memory system property crucial for achieving good performance under heap allocation is cache installation - the ability to allocate and initialize a new object into the cache without a penalty. Tracking heap initialization at a cache block granularity enables cache installation mechanisms to provide zero-latency prefetching into the cache. We propose a hardware mechanism, the allocation range cache, that can efficiently identify initializing store misses to the heap and trigger cache installations to avoid invalid memory traffic. The results obtained are presented and discussed

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Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on

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