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Design of compact high-frequency output buffer for testing of analog CMOS VLSI circuits

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3 Author(s)
VanPeteghem, P.M. ; Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA ; Duque-Carrillo, J.F. ; Liu, H.H.

A compact high-frequency CMOS analog buffer for testing purposes is presented. A prototype integrated in a 3-μm CMOS process drives a 15-pF, 10-kΩ load and shows a bandwidth of 25 MHz, a large-signal setting time to 1% of less than 90 ns, and a dynamic range over 77 dB. Power consumption is 2.4 mA per cell. Its small size (less than 0.18 mm 2) makes it suitable for monitoring low-capacitance internal nodes of analog or mixed-mode VLSI circuits

Published in:

Circuits and Systems, 1989., IEEE International Symposium on

Date of Conference:

8-11 May 1989

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