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The implementation of a module that performs radix-2 multiplication, division, and square root is presented. The module is compact because most of the components are shared by all three operations, the complexity being similar to that of a radix-2 divider. All three operations have the same execution time; one bit of the result is produced per cycle, beginning with the most significant bit. The cycle time is kept small by the use of carry-save addition and result-digit selection based on a low-precision estimate of the partial remainder. The module incorporates on-the-fly conversion and routing of the result
Published in:
Circuits and Systems, 1989., IEEE International Symposium on
Date of Conference: 8-11 May 1989
- Page(s):
- 150 - 153 vol.1
- Meeting Date :
- 08 May 1989-11 May 1989
- INSPEC Accession Number:
- 3624007
- Conference Location :
- Portland, OR
- Digital Object Identifier :
- 10.1109/ISCAS.1989.100314
- Product Type:
- Conference Publications
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