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The susceptibility of a self-aligned titanium silicide (salicide) process to the occurrence of conductive sidewall filaments is shown to depend upon the type of wafer cleans that are used prior to the titanium deposition. Aggressive cleans that are predominantly used for resist stripping were implemented immediately following the blanket plasma etch processes that define the sidewall nitride spacers on polysilicon gates. These cleans were effective in reducing the incidence of unwanted filaments between the polysilicon gates and the source/drain regions, as evidenced electrically using parametric test structures and physically via transmission electron microscopy (TEM) characterization. Two mechanisms to explain the efficacy of the cleans are hypothesized and discussed.