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An advanced methodology was implemented using intentionally created defect arrays to enhance the understanding of defect detection tools, thus improving yield learning. Intentional Defect Array (IDA) reticles were designed at International SEMATECH to target current and future ITRS requirements. Each IDA die pattern contains separate inspection areas for metal line widths of 0.18 μm, 0.25 μm, and 0.35 μm. Defect sizes at 25%, 50%, and 100% of the design feature size with known shapes and locations are placed in patterns of memory, logic, and electrical test arrays. Advanced lithographic capabilities, short-loop recipes, and dual damascene copper process flows were used to establish the IDA patterns on 200 mm wafers. The IDA wafers are being used in a variety of wafer inspection applications that require calculating capture and false count rates for defect detection. This paper describes the approach used for creating IDA wafers and the way these wafers can be applied to enhance product wafer yield.