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64-bit reconfigurable adder for low power media processing

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3 Author(s)
Perri, S. ; Dept. of Electron., Comput. Sci. & Syst., Calabria Univ., Italy ; Corsonello, P. ; Cocorullo, G.

A new, highly reconfigurable carry-skip adder for media signal processing is presented. The proposed circuit can be partitioned to perform one 64-, two 32-, four 16- and eight 8-bit additions. Partitioning is obtained without increasing the critical path. When the AMS 0.35 μm two-poly three-metal 3.3 V CMOS (CSD) process is used to produce the layout, the worst propagation delay and dissipation obtained is about 6.5 ns and 148 μW/ MHz

Published in:

Electronics Letters  (Volume:38 ,  Issue: 9 )