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Performance driven circuit clustering and partitioning

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2 Author(s)
Ling Wang ; Dept. of Electr. & Comput. Eng., Nevada Univ., Las Vegas, NV, USA ; Selvaraj, H.

In this paper, the problem of performance driven circuit partitioning is considered. The parameters taken into consideration to measure performance are power interconnection resource constraints. An algorithm is presented to build clusters in a bottom up manner while decomposing clusters for cutsize and delay minimization as well as power consumption and resource constraint. A partitioning method in a top down manner is applied based on the probability function.

Published in:

Information Technology: Coding and Computing, 2002. Proceedings. International Conference on

Date of Conference:

8-10 April 2002