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Direct mapping helps avoid algorithmic complexity which is inherent in logic synthesis methods. However, existing techniques for direct mapping of Petri net specifications to asynchronous control circuit do not deliver in performance due to logic overhead and inefficient interface to the environment. The paper presents a direct mapping method for Signal Transition Graphs (STGs) targetted at lower latency between input and output events. It is based on two behaviour-preserving transformations applied to the initial STG model: output exposition and environment tracking. The former allows interface signals to be generated concurrently to internal transitions. The latter prevents creation of coding conflicts. Subsequent refinement combines the use of the tracking and input signals in the control of the output flip-flops so as to optimise the circuit size by removing some tracking components. The depth of final logic in the design examples is one or two gates. The comparison to logic synthesis methods indicates lower output latency and greater size. The proposed direct-mapping method allows using fast transistor-level implementations for tracking and output signals with well-localised relative timing constraints.