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In this paper, a novel three-dimensional (3-D) BiCMOS technology is proposed and demonstrated. In this technology, the NMOS transistor is fabricated on the bulk substrate (bottom layer) and the PMOS transistor is fabricated on the single-crystal top layer obtained using the selective epitaxy growth (SEG) and lateral solid phase epitaxy (LSPE). In addition, the BJT is fabricated in the SEG region. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than that of the PMOS fabricated on SOI, and the BJTs also have high performance with a peak f/sub T/ of 17 GHz and f/sub max/ of 14 GHz at V/sub ce/=3 V. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuit applications.
Date of Publication: March 2002