By Topic

A novel 3-D BiCMOS technology using selective epitaxy growth (SEG) and lateral solid phase epitaxial (LSPE)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Liu, Haitao ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Clear Water Bay, China ; Kumar, M. ; Sin, J.K.O.

In this paper, a novel three-dimensional (3-D) BiCMOS technology is proposed and demonstrated. In this technology, the NMOS transistor is fabricated on the bulk substrate (bottom layer) and the PMOS transistor is fabricated on the single-crystal top layer obtained using the selective epitaxy growth (SEG) and lateral solid phase epitaxy (LSPE). In addition, the BJT is fabricated in the SEG region. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than that of the PMOS fabricated on SOI, and the BJTs also have high performance with a peak f/sub T/ of 17 GHz and f/sub max/ of 14 GHz at V/sub ce/=3 V. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuit applications.

Published in:

Electron Device Letters, IEEE  (Volume:23 ,  Issue: 3 )