Skip to Main Content
In this paper, the first 80 nm SON MOSFETs are presented, demonstrating the electrical viability of the SON architecture. The transistors have a 20 nm thick Si-film channel, isolated from the bulk by a 20 nm dielectric layer. The electrical results show significant improvement (/spl sim/30%) compared with bulk reference devices. In particular, drive current and transconductance are improved due to the better effective field-inversion charge compromise, and SCE due to the thinness of the junctions and of the channel. These electrical results are then used to calibrate the ISE simulator and to make predictions on SON performances with more aggressive gate length and Tox. These predictions show the potential of the SON architecture for future CMOS generations.