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Analysis of static and dynamic behaviour of SiC and Si devices connected in cascode configuration

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4 Author(s)
Mihaila, A. ; Dept. of Eng., Cambridge Univ., UK ; Udrea, F. ; Azar, R. ; Brezeanu, G.

This paper presents an analysis of the static and dynamic behaviour of a 1.2 kV SiC vertical JFET. The JFET can block voltages up to 1450 V (for VGS=80 V), with a specific on-resistance as low as 2.3 mΩcm2. The mixed-mode performance is investigated by coupling the SiC JFET in a cascode circuit with a low power Si MOSFET. Comparing the circuit performance to that of a SiC trench MOSFET, it turns out that the SiC/Si cascode is almost twice faster than the MOSFET. Coupling this with the fact that the SiC/Si cascode pair has better on-state performance, it is concluded that the cascode is a superior alternative to the classical SiC trench MOSFET

Published in:

Semiconductor Conference, 2001. CAS 2001 Proceedings. International  (Volume:2 )

Date of Conference:

Oct 2001

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