Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

A clustering utility based approach for ASIC design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Areibi, S. ; Sch. of Eng., Guelph Univ., Ont., Canada ; Thompson, M. ; Vannelli, A.

Due to the rapid growth of technologies, systems-on-chip (SoC) have started to become a key issue in today's electronics industry. In deep sub-micron designs, the interconnect is responsible for more than 90 percent of the signal delay in a chip. This paper presents a new approach for dealing with the high complexity of ASIC design. A new hierarchal clustering heuristic is presented that demonstrates excellent characteristics for reducing the execution time of standard-cell placement while achieving better results compared to non-clustered circuit placement methods. The clustering algorithm reduced the wire-length by 2% for small circuits and up to 10% for large circuits. Total execution time was reduced by more than 70% as expected

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference: