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A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique

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4 Author(s)
Yiwu Tang ; Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA ; Yingiie Zhou ; Bibyk, S. ; Ismail, M.

A new adaptation scheme for low noise and fast settling phase locked loops (PLLs) is presented. Extended loop bandwidth enhancement is achieved by the adaptive control on the reference frequency and frequency divide ratio. It enables the loop bandwidth in the speed-up mode to greatly exceed the limit of approximately 1/10 of the channel spacing in the integer frequency synthesizer. Based on the proposed adaptation scheme, a 450 MHz frequency synthesizer with a 200 kHz channel spacing is implemented in 0.5 μm CMOS process. In the speed-up mode, the loop bandwidth is enhanced by 16 times, resulting in a fast settling time of 260 μs to within 20 kHz for a 72 MHz frequency step by simulation

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001