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Utilizing memory bandwidth in DSP embedded processors

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1 Author(s)
Gebotys, C.H. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

This paper presents a network flow approach to solving the register binding and allocation problem for multi word memory access DSP processors. In recently announced DSP processors, such as Star*core, sixteen bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth (and up to 30% reduction in energy dissipation) are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can increase memory bandwidths and minimize code size without increasing cost.

Published in:

Design Automation Conference, 2001. Proceedings

Date of Conference:

2001