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For the last decade, the manufacturing cost per transistor has been exponentially decreasing. The test cost, however, has been decreasing at a much slower rate and now occupies a significant portion of the total cost of a microprocessor. To address this problem, many companies have planned to gradually move away from functional testing to less expensive structural and system level testing. The fundamental cost difference between these techniques comes from a reduction in the number of pins directly driven by the tester. This work describes a new technique that allows a tester to determine if all of the pins on a chip have acceptable leakage without requiring the tester to actually contact each individual pin.