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Two schemes to reduce interconnect delay in bi-directional and uni-directional buses

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2 Author(s)
Nose, K. ; Inst. of Ind. Sci., Tokyo Univ., Japan ; Sakurai, T.

As the device dimension is scaled down, interconnect RC delay becomes dominant performance limiter in high-performance VLSIs. Another issue in the submicron interconnects is a drastic increase of coupling capacitance due to the higher aspect ratio to reduce the interconnect resistance. The increase of the coupling capacitance degrades signal integrity, inducing noise problems and delay fluctuation problems. Buffer insertion (repeater insertion) is one of the most effective ways to decrease the interconnect delay. The original buffer insertion, however, cannot be applied to bi-directional buses because the buffer is uni-directional in nature. Some circuit configurations that can be applied to bi-directional buses have been proposed. These circuits turn out to be prone to malfunctions when there is a noise from adjacent lines in scaled down interconnect systems where capacitive coupling is large. A new buffer insertion scheme for bi-directional buses, namely the dual-rail bus (DRB) scheme, which does not have noise problems is proposed and measured in this paper. Another proposal is on a high-speed buffer insertion scheme for uni-directional buses by making use of staggered firing. The staggered firing bus (SFIB) is proposed and measured.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001