Referenced Items are not available for this document.
To achieve high yield products without degrading the performance, it is important to optimize the device condition, considering the process variation. We present a model parameter extraction methodology to extract the process variation from the E-T (Electrical Test) data. We have estimated the parametric yield of a 0.20 /spl mu/m process SRAM test chip using Monte Carlo simulation and have obtained good agreement compared to measurement. We also performed device optimization using a critical path to improve the parametric yield.
Published in:
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Date of Conference: 14-16 June 2001
- Page(s):
- 163 - 166
- Meeting Date :
- 14 Jun 2001-16 Jun 2001
- Print ISBN:
- 4-89114-014-3
- INSPEC Accession Number:
- 7081212
- Conference Location :
- Kyoto, Japan
- Digital Object Identifier :
- 10.1109/VLSIC.2001.934227
- Product Type:
- Conference Publications
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