Skip to Main Content
In order to improve cell array efficiency and reference voltage characteristics of ITlC FeRAM, two key techniques are proposed in this paper. 1) Cell operation scheme with pulse-tuned signals on wordline and plateline for achieving uniform bitline levels in short time and 2) reference voltage generation scheme using dual pulse control for reference voltage to track variable bitline sensing voltage in wide range of operation voltage and temperature. 2Mb ITlC FeRAM in unit block of 512 rows by 256 columns cell array with 0.35pm design rule are implemented. The optimized uniform bitline sensing voltage and reference voltage are achieved at the condition of the first wordline pulse signal of 3011s and the reference dual pulse signal time of 30-4011s at 3V in room temperature.
Date of Conference: 14-16 June 2001