Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications

A 16.3 mW low power motion compensation (MC) block IP with 1.25 Mbit embedded DRAM macro is implemented using 0.18 /spl mu/m EML technology for portable video applications. For low power consumption, its frequency is lowered to 20 MHz by utilizing parallelism in datapath. Embedded DRAM frame buffer eliminates external data I/O. In addition, distributed nine-tiled mapping (DNTM) with partial activation scheme reduces power for accessing the frame buffer up to 31% compared to conventional 1-bank tiled mapping. Adaptive fetch control (AFC) in data buffer reduces power up to 29% by eliminating unnecessary switching in datapath.