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A 120 mW embedded 3D graphics rendering engine with 6 Mb logically local frame-buffer and 3.2 GByte/s run-time reconfigurable bus for PDA-chip

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7 Author(s)
Ramchan Woo ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Chi-Weon Yoon ; Jeonghoon Kook ; Se-Joong Lee
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An embedded 3D graphics rendering engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001