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Two design techniques are presented to improve the yield of high density DRAM product. One is bit line coupling (BLC) scheme and the other is electrical fuse (E-Fuse) circuit for reliable field programmable repair scheme. We obtain an improvement of 100 ms for the data retention time (tREF) using the BLC scheme. BLC scheme also improves the low VCC margin by 0.3 V and the RAS to CAS delay time (tRCD) by 1.5 ns. Differential current evaluation for the E-fuse implementation shows polysilicon fuse fail rate <10/sup -12/.
Date of Conference: 14-16 June 2001