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A hardmask STI etch process for 0.13 μm logic technology and beyond

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9 Author(s)
Wong, J. ; IBM Corp., Essex Junction, VT, USA ; Weil, J. ; Whiting, C. ; Chien Yu
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Shallow trench isolation (STI) is a standard device isolation process for geometries smaller than 0.25 μm. The traditional STI etch pattern transfer process has used a relatively thick resist stack (>600 nm) to accommodate the low silicon-to-resist etch selectivity in the traditional soft mask STI etch. As ground rules shrink, lithographic depth of focus (DOF), a key driver for manufacturability, decreases as a result of increases in tool numerical aperture (NA) and shorter illumination wavelength (λ). One way to increase DOF is to decrease the photoresist thickness, but this can require substantial chemistry changes in the etch process to improve selectivity. Emerging technologies call for thinner resist stacks to widen the lithographic process window, while at the same time requiring the ability to etch a deeper STI trench. We present an alternative STI etch process not usually used in isolation levels, one which allows for a wider DOF and deeper STI trench, suitable for 0.13 μm logic technology and beyond

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Advanced Semiconductor Manufacturing Conference, 2001 IEEE/SEMI

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