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Design of GHz VLSI clock distribution circuit

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2 Author(s)
Zeng, X. ; Dept. of Electr. Eng., Fudan Univ., Shanghai, China ; Zhou, D.

In this paper, we derive a formula for running the clock signal in a pipeline fashion to meet the GHz frequency challenge. Moreover we present an optimal algorithm for simultaneous balanced planar tree routing and optimal buffer insertion to reach the GHz limit. To ensure the signal integrity, we have developed a very efficient transmission line based simulator, which plays a key role in verifying the clock circuit performance. The proposed method is successfully used to design a real industrial GHz CPU

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2001