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A cutting algorithm for optimizing the wafer exposure pattern

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3 Author(s)
Chen-Fu Chien ; Dept. of Ind. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Shao-Chung Hsu ; Jing-Feng Deng

Semiconductor manufacturing industry competes by increasing yield and lowering die costs, thereby taking advantage of significant capital investments. Many studies focus on defect reduction to improve yield rate. However, the problem of optimizing wafer exposure patterns has received little attention. In this paper, given the specific patterning constraints, we develop a two-dimensional (2-D) cutting algorithm to maximize the gross die yields of the eight-inch wafer and larger circular wafers. The empirical results that we implemented in a wafer fabrication factory in Taiwan validate the practical viability of this approach. Similar approaches can readily be applied to other wafer patterning

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:14 ,  Issue: 2 )