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A 12.5 ns 16 Mb CMOS SRAM

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13 Author(s)
Ishibashi, K. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Komiyaji, K. ; Morita, S. ; Aoto, T.
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A high-speed circuit, a high-yield redundancy technique, and a soft-error immune cell are essential to realize ultra high density static RAMs. A 16 Mb (4Mx4/2Mx8) CMOS SRAM fabricated using 0.4 /spl mu/m CMOS technology is reported. An address access time of 12.5 ns is attained with 3.3 V supply voltage by using a common-centroid-geometry (CCG) layout sense amplifier and divided data bus architecture. A flexible redundancy technique (FRT) with high efficiency and with no access penalty has been incorporated into the 16 Mb SRAM. A 7.16 /spl mu/m/sup 2/ TFT load cell with stacked capacitors, achieves soft-error immunity even for the supply voltage of 3.3 V.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993